1. Technical Field
The present invention relates to semiconductor devices and manufacturing processes, and more particularly to methods and arrangements associated with a multipurpose graded silicon oxynitride cap layer in non-volatile memory semiconductor devices.
2. Background Art
A continuing trend in semiconductor technology is to build integrated circuits with more and/or faster semiconductor devices. The drive toward this ultra large-scale integration (ULSI) has resulted in continued shrinking of devices and circuit features. As the devices and features shrink, new problems are discovered that require new methods of fabrication and/or new arrangements.
A flash or block erase Electrically Erasable Programmable Read Only Memory (flash EEPROM) semiconductor memory includes an array of memory cells that can be independently programmed and read. The size of each memory cell, and therefore the memory array is reduced by a omitting select transistors that would enable the cells to be erased independently. The array of memory cells is typically aligned along a bit line and a word line and erased together as a block. An example of a memory of this type includes individual metal oxide semiconductor (MOS) memory cells, each of which includes a source drain, floating gate, and control gate to which various voltages are applied to program the cell with a binary 1 or 0. Each memory cell can be read by addressing it via the appropriate word and bit lines.
An exemplary memory cell 8 is depicted in FIG. 1A, viewed in a cross-section through the bit line. Memory cell 8 includes a doped substrate 12 having a top surface 11, and a source 13A and a drain 13B formed by selectively doping regions of substrate 12. A tunnel oxide 15 separates a floating gate 16 from substrate 12. An interpoly dielectric 24 separates floating gate 16 from a control gate 26. Floating gate 16 and control gate 26 are each electrically conductive and typically formed of polysilicon.
On top of control gate 26 is a silicide layer 28, which acts to increase the electrical conductivity of control gate 26. Silicide layer 28 is typically a tungsten silicide (e.g., WSi2), that is formed on top of control gate 26 prior to patterning, using conventional deposition and annealing processes.
As known to those skilled in the art, memory cell 8 can be programmed, for example, by applying an appropriate programming voltage to control gate 26. Similarly, memory cell 8 can be erased, for example, by applying an appropriate erasure voltage to source 13A. When programmed, floating gate 16 will have a charge corresponding to either a binary 1 or 0. By way of example, floating gate 16 can be programmed to a binary 1 by applying a programming voltage to control gate 26, which causes an electrical charge to build up on floating gate 16. If floating gate 16 does not contain a threshold level of electrical charge, then floating gate 16 represents a binary 0. During erasure, the charge is removed from floating gate 16 by way of the erasure voltage applied to source 13B.
FIG. 1B depicts a cross-section of several adjacent memory cells from the perspective of a cross-section through the word line (i.e., from perspective A, as referenced in FIG. 1A). In FIG. 1B, the cross-section reveals that individual memory cells are separated by isolating regions of silicon dioxide formed on substrate 12. For example, FIG. 1B shows a portion of a floating gate 16a associated with a first memory cell, a floating gate 16b associated with a second memory cell, and a floating gate 16c associated with a third memory cell. Floating gate 16a is physically separated and electrically isolated from floating gate 16b by a field oxide (FOX) 14a. Floating gate 16b is separated from floating gate 16c by a field oxide 14b. Floating gates 16a, 16b, and 16c are typically formed by selectively patterning a single conformal layer of polysilicon that was deposited over the exposed portions of substrate 12, tunnel oxide 15, and field oxides 14a and 14b. Interpoly dielectric layer 24 has been conformally deposited over the exposed portions of floating gates 16a, 16b, and 16c and field oxides 14a and 14b. Interpoly dielectric layer 24 isolates floating gates 16a, 16b and 16c from the next conformal layer which is typically a polysilicon layer that is patterned (e.g., along the bit line) to form control gate 26. Interpoly dielectric layer 24 typically includes a plurality of films, such as, for example, a bottom film of silicon dioxide, a middle film of silicon nitride, and a top film of silicon dioxide. This type of interpoly dielectric layer is commonly referred to as an oxide-nitride-oxide (ONO) layer.
The continued shrinking of the memory cells, and in particular the basic features depicted in the memory cells of FIGS. 1A and 1B, placed a burden on the fabrication process to deposit and subsequently pattern a layer stack to form a floating gate/control gate structure, without creating deleterious effects within the resulting memory cells. In particular, conventional photolithography techniques using deep ultraviolet (DUV) lithography techniques has a limit on the order of about 0.25 microns resist line widths. Hence, the size of the memory gate generally has been limited to the capabilities of the DUV photolithography techniques.
One technique commonly used in logic processes used to form logic circuits is trimming the resist pattern. Specifically, the technique is used for logic processes, where the resist pattern is etched to trim the resist pattern, causing a reduction in the resist line width of up to 0.1 microns. However, the resist cannot be trimmed any more than 0.1 microns due to the accumulation of polymers during the etching along the edges of the trim. Hence, a logic mask can be trimmed by up to 0.1 microns, for example reduced from a width of 0.28 microns to 0.18 microns.
The resist trim process in the logic processes, however, is not practicable in etching of memory gates, since the number of layers etched in logic processes is substantially less than in memory gate etching. Logic processes require a resist thickness of about 2,000 Angstroms, whereas the thickness required for etching the plurality of layers used to form a memory gate is about 8,000-9,000 Angstroms. In addition, there is a concern in memory processes of resolution in both line and space, as opposed to logic processes. Moreover, there is a concern of accumulation of the polymers during etching. Hence, etching of the resist mask may result in loss of the mask pattern during memory gate etching.
There is a need for an arrangement that enables memory gate sizes to be reduced in a manner that overcomes the existing limits of conventional DUV lithography techniques.
There is also a need for an arrangement that enables a resist mask pattern to be trimmed, while enabling the mask pattern to be preserved for memory gate etching.
These and other needs are attained by the present invention, where a resist mask pattern is formed overlying on an antireflective coating layer formed on a semiconductor wafer having a plurality of layers. The sidewalls of the resist mask pattern lines are first etched to a first prescribed reduced width, and then the antireflective coating layer is etched based on the etched resist mask pattern lines. The etching of the antireflective coating layer forms etched antireflective coating layer pattern lines that have a width less than the width of the etched sidewalls of the resist mask pattern lines.
According to one aspect of the present invention, a method of etching a semiconductor wafer having a plurality of layers to form a memory gate stack comprises forming a resist mask pattern, having pattern lines, overlying on an antireflective coating layer formed on the semiconductor wafer, first etching sidewalls of the resist mask pattern lines to a first prescribed reduced width, second etching the antireflective coating layer, based on the etched resist mask pattern lines, to form etched antireflective coating layer pattern lines having a second prescribed reduced width less than the first reduced width, and third etching the plurality of layers underlying the antireflective coating layer based on the etched antireflective coating layer pattern lines. Etching of the antireflective coating layer enables the resist mask pattern lines having the first prescribed reduced width to be transferred to the antireflective coating layer. In addition, the second etching enables further width reduction of the pattern lines, enabling the plurality of layers underlying the antireflective coating layer to be etched based on the etched antireflective coating layer pattern. Hence, a memory gate can be formed that has a width substantially less than the current photolithography limit during formation of the resist mask pattern.
Another aspect of the present invention provides a method of etching a semiconductor wafer, having a plurality of layers and an antireflective coating layer overlying on the plurality of layers, using a resist mask pattern formed on the antireflective coating layer and having a minimum resist line width of about 0.25 microns comprising etching the resist mask pattern to a maximum etched resist line width of about 0.20 microns, and etching the antireflective coating layer based on the etched resist mask pattern to form an etched antireflective coating layer having maximum line widths of about 0.18 microns, wherein the etched antireflective coating layer is used to etch the plurality of layers to form a memory gate stack. The etching of the antireflective coating layer enables further reduction in the resist mask pattern by removing polymers that normally accumulate during the etching of the resist mask pattern. Moreover, the etching of the antireflective coating layer based on the etched resist mask pattern enables formation of line widths less than or equal to 0.18 microns using 0.25 micron lithography technology, where the plurality of layers underlying the etched antireflective coating layer can be etched to form memory gate structures having widths of about 0.18 microns or less.
Additional objects, advantages and novel features of the invention will be set forth in part in the description which follows, and in part may become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.